Dynamic random access memory (DRAM) devices can employ cell capacitors to store data. Attempts to increase the density of DRAM devices have typically resulted in the decrease of the area that the cell capacitors occupy. As a result, the capacitance of the cells may be reduced in proportion to the respective cell area. If cell capacitance is reduced too much, data stored in the cells may be lost due to alpha particles. Accordingly, the cell capacitance should be maintained to guard against the potential loss of data and to generally improve the characteristics of the cells in such highly integrated DRAMs. It is known to use dielectric layers having a high dielectric constant in DRAM devices to increase the cell capacitance.
FIGS. 1 through 3 are cross-sectional views that illustrate a method of fabricating a conventional semiconductor device. Referring to FIG. 1, a lower interlayer insulating layer 3 is formed on a semiconductor substrate 1. A bottom electrode contact plug 5 is formed in the lower interlayer insulating layer 3 and penetrates a predetermined region of the lower interlayer insulating layer 3. A bottom electrode 7 is formed on the lower interlayer insulating layer 3 to cover the bottom electrode contact plug 5. A dielectric layer 9 is formed on an entire surface of the semiconductor substrate 1 having the bottom electrode 7. The dielectric layer 9 is formed of a tantalum oxide layer (Ta2O5) having a dielectric constant that is greater than that of a silicon nitride layer. The substrate and the dielectric layer 9 is then annealed to crystallize the dielectric layer 9. As a result, the dielectric layer 9, (i.e., the tantalum oxide layer) has a high dielectric constant of about 20 to 30.
Referring to FIG. 2, a top electrode 11 is formed on the annealed dielectric layer 9. The top electrode 11 is formed of a conductive layer that has strong oxidation resistance. For example, the top electrode 11 may be formed of a platinum layer or a ruthenium layer. The substrate including the top electrode 11 is annealed in an oxygen atmosphere to remove or reduce oxygen vacancies from the dielectric layer 9. During this annealing process, oxygen atoms may penetrate the top electrode 11 (from the dielectric layer 9) thereby increasing the quantity of oxygen atoms in the top electrode 11. An upper interlayer insulating layer 13 is formed on the top electrode 11 after the oxygen annealing process.
Referring to FIG. 3, the upper interlayer insulating layer 13 is patterned to form a metal contact hole 15 that exposes a predetermined region of the top electrode 11. An ohmic metal layer 17 and a barrier metal layer 19 are sequentially formed on an entire surface of the substrate including the metal contact hole 15. A titanium layer is widely used as the ohmic metal layer 17. The titanium atoms in the ohmic metal layer 17 may react with the oxygen atoms in the top electrode 11, thereby generating an insulating layer, such as a titanium oxide layer 21, at an interface between the ohmic metal layer 17 and the top electrode layer 11 which may increase the contact resistance between the ohmic metal layer 17 and the top electrode layer 11.